Flip-flop circuits are essential components in any digital system design and are used in almost all integrated circuits that are manufactured. Flip-flop circuits are normally used to store data that is a result of a computation performed by a digital circuit or they are used to sequence data in an integrated circuit in order to facilitate some manner of computation.
Binary flip-flops are flip-flop circuits that store two possible signal levels, logic low and logic high. All signals that are applied to the flip-flop circuits can be considered to have the aforementioned two possible logic levels.
There are two distinct approaches to such conventional flip-flop design. The first approach uses gate-level design i.e. individual functional logic gates such as NAND, NOR, AND, OR or INVERSION are used to achieve edge-triggering effect. These solutions are static gates and have high device count as well as low speed of operation. They are, however, very reliable and robust.
The second approach uses a dynamic or pseudo-static flip-flop implementation. These are more compact and faster implementations of a flip-flop as compared to the static approach. However, the dynamic nature of these circuits makes them less reliable. The latter approach to flip-flop design, however, is most prevalent in state-of-the-art ICs that constantly aim to push circuit operation at greater speeds.
One important characteristic of edge-triggered flip-flop circuits is that data presented at the input of the circuit or as determined by the flip-flop control signals such as S-R or T is reflected at the output of the circuit either on the low-to-high transition (positive edge-trigger) or the high-to-low (negative edge-trigger) transition of a clocking signal.
In general, the ideal behavior of a flip-flop circuit would be to act as a storage element but not introduce additional delay in the signal path in which the flip flop is inserted, and to not consume any circuit area in doing so. It is well known that the real life behavior of flip-flop circuits is non-ideal as a result of which flip-flop circuits do cause delay and area overhead in integrated circuits. Thus, one of the objectives of a flip-flop design is to reduce its delay and area. Also, the non-ideal behavior of flip-flop circuits dictates that the input signals to the flip-flop be held a constant value for a small window around the edge of the clocking signal. It is also a criterion of flip-flop circuit design to reduce this window to a very small fraction of the total period of the clocking signal.
NDR diodes such as resonant tunneling diodes (RTDs) have been used to design high-speed and compact digital logic circuits due to their picosecond switching speeds and folded current vs. voltage characteristics. While latching storage circuits can be built efficiently due to the inherent bistability in the NDR diode characteristics, such circuits use level-sensitive clocking signals, i.e. any change in the input when the clocking signal is active (be it high or low) is reflected at the output. Thus, in order for the circuit to function correctly, input data must be maintained for the entire duration of the active portion of the clocking signal and not just in a small window around the active transition edge of the clocking signal.
The time period for which the data needs to be constant before the active clock edge is called the setup time and the time period for which the data needs to be held constant after the active clock edge is called the hold time. There are no known implementations of edge-triggered flip-flop circuits using NDR diodes.
Prior art U.S. patents, generally relevant the present invention include: U.S. Pat. Nos. 4,057,741; 4,140,924; 4,656,368; and 5,189,315.
A prior art article also generally relevant to the present invention is: J. Yuan and C. Svensson, "High-Speed CMOS Circuit Technique", IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 24, No. 1, February 1989, pp. 62-70.